Master-slave clock generation circuit
US10270433B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2018 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Mar 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In various embodiments, a master-slave clock generation circuit may include a first delay circuit, a second delay circuit, a first tristate inverter, and a second tristate inverter. The first delay circuit may delay a clock signal and output a slave clock signal and a delayed clock signal. The first tristate inverter may selectively invert the clock signal based on a scan enable signal. The second tristate inverter may selectively invert the delayed clock signal based on the scan enable signal. The second delay circuit may delay a signal received from the first tristate inverter, the second tristate inverter, or both, and output a master clock signal. As a result, the master-slave clock generation circuit may be configured to output a master clock signal and a slave clock signal having differing sets of relative timing characteristics depending on whether the scan enable signal is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.