Inventor · San Jose, CA, US

Vivekanandan Venugopal

26Patents
4h-index
15Co-inventors
52Inventor score

Filing activity: Jun 16, 2017 → May 26, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US10187061B1 Level shifting circuit with data resolution and grounded input nodes Electricity 8 Active
US11005459B1 Efficient retention flop utilizing different voltage domain Electricity 6 Active
US10581412B1 Pulsed level shifter circuitry Electricity 4 Active
US10461747B2 Low power clock gating circuit Electricity 4 Active
US11018653B1 Low voltage clock swing tolerant sequential circuits for dynamic power savings Emerging Cross-Sectional Technologies 2 Active
US10261563B1 Hybrid power switch Emerging Cross-Sectional Technologies 2 Active
US10742201B2 Hybrid pulse/master-slave data latch Emerging Cross-Sectional Technologies 2 Active
US10838483B2 Level shifter with isolation on both input and output domains with enable from both domains Emerging Cross-Sectional Technologies 1 Active
US11418174B2 Efficient retention flop utilizing different voltage domain Electricity 1 Active
US12334146B1 Power loss reduction in data storage arrays Physics 0 Active
US10732693B2 Hybrid power switch Emerging Cross-Sectional Technologies 0 Active
US11164611B1 Level-shifting transparent window sense amplifier Physics 0 Active
US11336272B2 Low power single retention pin flip-flop with balloon latch Electricity 0 Active
US11870442B2 Hybrid pulse/two-stage data latch Emerging Cross-Sectional Technologies 0 Active
US11424734B2 Low voltage clock swing tolerant sequential circuits for dynamic power savings Emerging Cross-Sectional Technologies 0 Active
US11418173B2 Hybrid pulse/two-stage data latch Emerging Cross-Sectional Technologies 0 Active
US11303268B2 Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges Electricity 0 Active
US10270433B1 Master-slave clock generation circuit Physics 0 Active
US10491197B2 Flop circuit with integrated clock gating circuit Electricity 0 Active
US11139803B1 Low power flip-flop with balanced clock-to-Q delay Electricity 0 Active
US11132010B1 Power down detection for non-destructive isolation signal generation Physics 0 Active
US11496120B2 Flip-flop circuit with glitch protection Electricity 0 Active
US10734040B1 Level-shifting transparent window sense amplifier Physics 0 Active
US11258446B2 No-enable setup clock gater based on pulse Electricity 0 Active
US10903824B2 Pulsed level shifter circuitry Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.