Coarse-fine quantization architecture for multiphase VCO-based ADCs
US10270460B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2018 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Jun 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/466
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter includes a ring oscillator having an input for receiving an analog signal, a coarse Gray code counter having a first input coupled to a first output of the ring oscillator and a second input for receiving a clock signal, a fine counter having first inputs coupled to secondary outputs of the ring oscillator and a second input for receiving the clock signal, a first difference generator having an input coupled to the output of the coarse counter, a second difference generator having an input coupled to the output of the fine counter, and an adder having a first input coupled to the output of the first difference generator, a second input coupled to the output of the second difference generator, and an output for providing a digital signal corresponding to the analog signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.