SRAM cell for interleaved wordline scheme
US10276231B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2018 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Feb 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.