Mahmut Sinangil
36Patents
4h-index
28Co-inventors
59Inventor score
Filing activity: Dec 10, 2012 → Nov 10, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9208900B2 | System and method for performing address-based SRAM access assists | Physics | 13 | Active |
| US8861290B2 | System and method for performing SRAM write assist | Physics | 13 | Active |
| US10803928B2 | Low voltage memory device | Physics | 8 | Active |
| US9418714B2 | Sense amplifier with transistor threshold compensation | Physics | 5 | Active |
| US9886996B2 | SRAM cell for interleaved wordline scheme | Electricity | 4 | Active |
| US10847214B2 | Low voltage bit-cell | Physics | 4 | Active |
| US9922700B2 | Memory read stability enhancement with short segmented bit line architecture | Physics | 4 | Active |
| US11404114B2 | Low voltage memory device | Physics | 2 | Active |
| US11322195B2 | Compute in memory system | Electricity | 2 | Active |
| US10153038B2 | Memory read stability enhancement with short segmented bit line architecture | Physics | 2 | Active |
| US11238906B2 | Series of parallel sensing operations for multi-level cells | Physics | 2 | Active |
| US10770131B2 | SRAM cell for interleaved wordline scheme | Electricity | 1 | Active |
| US10510403B2 | Memory read stability enhancement with short segmented bit line architecture | Physics | 1 | Active |
| US12131800B2 | Physically unclonable cell using dual-interlocking and error correction techniques | Physics | 1 | Active |
| US9762216B1 | Level shifter circuit using boosting circuit | Electricity | 1 | Active |
| US11763882B2 | Low voltage memory device | Physics | 1 | Active |
| US9245601B2 | High-density latch arrays | Electricity | 0 | Active |
| US10410715B2 | Pre-charging bit lines through charge-sharing | Physics | 0 | Active |
| US11848047B2 | Pre-charging bit lines through charge-sharing | Physics | 0 | Active |
| US9922701B2 | Pre-charging bit lines through charge-sharing | Physics | 0 | Active |
| US11562779B2 | Bit line secondary drive circuit and method | Physics | 0 | Active |
| US10276231B2 | SRAM cell for interleaved wordline scheme | Electricity | 0 | Active |
| US12272420B2 | Series of parallel sensing operations for multi-level cells | Physics | 0 | Active |
| US12300312B2 | Pre-charging bit lines through charge-sharing | Physics | 0 | Active |
| US12073869B2 | Compute in memory system | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.