Programming NAND flash with improved robustness against dummy WL disturbance
US10276250B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Nov 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.