MACRONIX INTERNATIONAL CO., LTD.
3,589Patents
2,536Active
3,589Granted
60Portfolio score
Filing activity: Sep 5, 1990 → May 6, 2024 · 897 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8076230B2 | Method of forming self-aligned contacts and local interconnects | Electricity | 527 | Active |
| US6579760B1 | Self-aligned, programmable phase change memory | Electricity | 320 | Expired |
| US6320786A | Method of controlling multi-state NROM | Physics | 314 | Expired |
| US8203187B2 | 3D memory array arranged for FN tunneling program and erase | Electricity | 294 | Active |
| US8208279B2 | Integrated circuit self aligned 3D memory array and manufacturing method | Electricity | 289 | Active |
| US7688619B2 | Phase change memory cell and manufacturing method | Physics | 282 | Active |
| US7608848B2 | Bridge resistance random access memory device with a singular contact structure | Electricity | 272 | Active |
| US7229502B2 | Method of forming a silicon nitride layer | Electricity | 266 | Expired |
| US7450423B2 | Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure | Electricity | 264 | Active |
| US7697316B2 | Multi-level cell resistance random access memory with metal oxides | Electricity | 264 | Active |
| US6487114B2 | Method of reading two-bit memories of NROM cell | Physics | 263 | Expired |
| US7786460B2 | Phase change memory device and manufacturing method | Physics | 256 | Active |
| US7586778B2 | Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states | Physics | 256 | Active |
| US5526307A | Flash EPROM integrated circuit architecture | Electricity | 246 | Expired |
| US6864503B2 | Spacer chalcogenide memory method and device | Emerging Cross-Sectional Technologies | 231 | Expired |
| US7447068B2 | Method for programming a multilevel memory | Physics | 231 | Active |
| US6177317A | Method of making nonvolatile memory devices having reduced resistance diffusion regions | Electricity | 228 | Expired |
| US5956473A | Method and system for managing a flash memory mass storage system | Physics | 222 | Expired |
| US6271090A | Method for manufacturing flash memory device with dual floating gates and two bits per cell | Electricity | 221 | Expired |
| US6734107B2 | Pitch reduction in semiconductor fabrication | Electricity | 218 | Expired |
| US6638441B2 | Method for pitch reduction | Emerging Cross-Sectional Technologies | 214 | Expired |
| US7220983B2 | Self-aligned small contact phase-change memory method and device | Electricity | 206 | Expired |
| US9589982B1 | Structure and method of operation for improved gate capacity for 3D NOR flash memory | Physics | 203 | Active |
| US5754469A | Page mode floating gate memory device storing multiple bits per cell | Physics | 198 | Expired |
| US6955961B1 | Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution | Emerging Cross-Sectional Technologies | 196 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.