Semiconductor package and manufacturing process thereof
US10276402B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2016 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | May 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06572
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.