Semiconductor device substrate, semiconductor device wiring member and method for manufacturing them, and method for manufacturing semiconductor device using semiconductor device substrate
US10276422B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Dec 25, 2015 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Dec 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device substrate and wiring member including a first noble metal plating layer to become internal terminals is formed at predetermined sites on a metal plate, a metal plating layer is formed on the first noble metal plating layer as having a same shape as the first noble metal plating layer, a second noble metal plating layer to become external terminals is formed on a part of the metal plating layer, and a height of a surface of the second noble metal plating layer from a surface of the metal plate is larger than a height of a surface of the first noble metal plating layer from the surface of the metal plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.