Circuits constructed from stacked field-effect transistors
US10276453B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2018 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Mar 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures that include vertically-arranged field-effect transistors and methods for forming a structure that includes vertically-arranged field-effect transistors. A first field-effect transistor includes a section of a first fin, a first source/drain region, and a second source/drain region. The section of the first fin is arranged between the first source/drain region and the second source/drain region of the first field-effect transistor. A second field-effect transistor includes a second fin arranged over the section of the first fin, a first source/drain region, and a second source/drain region. A functional gate structure has an overlapping arrangement with the section of the first fin and also has an overlapping arrangement with a section of the second fin that is arranged between the first source/drain region and the second source/drain region of the second field-effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.