Integrated standard cell structure
US10276554B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2018 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Jun 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
Abstract
An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and having a one-pitch dimension P. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region. The first filler cell includes a third dielectric gate on a first filler cell boundary and a fourth dielectric gate on a second filler cell boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.