Semiconductor memory device
US10276585B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Jul 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06517
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.