Memory cell, semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device
US10276727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2016 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | May 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.