Memory device and fabrication method thereof

US10276794B1 · kind B1 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Tai-Yen Peng · Hsinchu, TW
• Hui-Hsien Wei · Taoyuan, TW
• Wei-Chih Wen · Hsinchu, TW
• Pin-Ren Dai · New Taipei, TW
• Chien-Min Lee · Hsinchu, TW
• Han-Ting Tsai
• Jyu-Horng Shieh · Hsinchu, TW
• Chung-Te Lin · Tainan, TW

Key dates

• Filing date: Oct 31, 2017
• Grant date: Apr 30, 2019
• Expiry date: Oct 31, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8833

Abstract

A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.