Inventor · Tainan, TW

Chung-Te Lin

299Patents
12h-index
171Co-inventors
89Inventor score

Filing activity: Mar 25, 1998 → Apr 11, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US6057207A Shallow trench isolation process using chemical-mechanical polish with self-aligned nitride mask on HDP-oxide Electricity 32 Expired
US6063695A Simplified process for the fabrication of deep clear laser marks using a photoresist mask Emerging Cross-Sectional Technologies 32 Expired
US6444544B1 Method of forming an aluminum protection guard structure for a copper metal structure Electricity 31 Expired
US10522642B2 Semiconductor device with air-spacer Electricity 23 Active
US7432149B2 CMOS on SOI substrates with hybrid crystal orientations Electricity 19 Active
US11171157B1 Method for forming a MFMIS memory device Electricity 18 Active
US6194285A Formation of shallow trench isolation (STI) Electricity 18 Expired
US6287926A Self aligned channel implant, elevated S/D process by gate electrode damascene Electricity 16 Expired
US11423966B2 Memory array staircase structure Electricity 15 Active
US9336348B2 Method of forming layout design Electricity 13 Active
US6444541B1 Method for forming lining oxide in shallow trench isolation incorporating pre-annealing step Electricity 13 Expired
US9899263B2 Method of forming layout design Electricity 12 Active
US10644231B2 Memory device and fabrication method thereof Electricity 11 Active
US10276794B1 Memory device and fabrication method thereof Electricity 11 Active
US10991756B2 Bipolar selector with independently tunable threshold voltages Physics 10 Active
US9431381B2 System and method of processing cutting layout and example switching circuit Physics 10 Active
US9412700B2 Semiconductor device and method of manufacturing semiconductor device Electricity 10 Active
US11355516B2 Three-dimensional memory device and method Electricity 8 Active
US6207538A Method for forming n and p wells in a semiconductor substrate using a single masking step Electricity 8 Expired
US10756174B2 Multiple-stacked semiconductor nanowires and source/drain spacers Electricity 7 Active
US10170378B2 Gate all-around semiconductor device and manufacturing method thereof Electricity 7 Active
US6103581A Method for producing shallow trench isolation structure Electricity 7 Expired
US6080638A Formation of thin spacer at corner of shallow trench isolation (STI) Electricity 7 Expired
US7943961B2 Strain bars in stressed layers of MOS devices Electricity 7 Active
US6074905A Formation of a thin oxide protection layer at poly sidewall and area surface Electricity 7 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.