Efficient preemption for graphics processors
US10282227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2014 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Aug 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods may provide for inserting one or more preemption instructions while compiling a computer program. The one or more preemption instructions being inserted within a preemption window in the computer program reduces the number of live registers at each preemption instruction position. Further, the preemption instruction instructs which registers are to be saved at a particular program position, typically the registers that are live at that program position. The compiled program may be run in an execution unit. A preemption request may be made to the execution unit and executed at a next available preemption instruction in the program being run in the execution unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.