Kaiyu Chen
11Patents
4h-index
25Co-inventors
56Inventor score
Filing activity: Nov 29, 2007 → Jun 24, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10282227B2 | Efficient preemption for graphics processors | Physics | 6 | Active |
| US10360654B1 | Software scoreboard information and synchronization | Physics | 5 | Active |
| US7585705B2 | Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop | Electricity | 5 | Active |
| US8084304B2 | Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop | Electricity | 4 | Active |
| US7728385B2 | Trench MOSFET with an ONO insulating layer sandwiched between an ESD protection module atop and a semiconductor substrate | Electricity | 2 | Active |
| US10515431B2 | Global optimal path determination utilizing parallel processing | Emerging Cross-Sectional Technologies | 1 | Active |
| US10565670B2 | Graphics processor register renaming mechanism | Physics | 1 | Active |
| US10699362B2 | Divergent control flow for fused EUs | Physics | 0 | Active |
| US10692170B2 | Software scoreboard information and synchronization | Physics | 0 | Active |
| US12174783B2 | Systolic array of arbitrary physical and logical depth | Physics | 0 | Active |
| US10636112B2 | Graphics processor register data re-use mechanism | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.