Method and system for hardware accelerated read-ahead caching
US10282301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Jun 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for efficient cache buffering are provided. The disclosed method determining that a read-ahead operation is to be performed in response to receiving a host Input/Output (I/O) command. In response to determining that the read-ahead operation is to be performed, allocating a new Local Message Identifier (LMID) for the read-ahead operation. The method further includes sending a buffer allocation request to a buffer manager module, the buffer allocation request containing parameters associated with the read-ahead operation and then causing the buffer manager module to allocate at least one Internal Scatter Gather List (ISGL) and Buffer Section Identifier (BSID) in accordance with the parameters contained in the buffer allocation request. The method further includes enabling the cache manager module to perform a hash search using a row or strip number and identification information available in the new LMID.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.