Patent · US Active

Supporting secure memory intent

US10282306B2 · kind B2 · utility

4Cited by
18References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 3, 2018
Grant dateMay 7, 2019
Priority date
Expiry dateJan 3, 2038

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02D10/00
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.