Mitigating length-of-diffusion effect for logic cells and placement thereof
US10282503B2 · kind B2 · utility
3Cited by
5References
30Claims
0Family size
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Key dates
| Filing date | Jun 25, 2016 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Jun 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods relate to cell placement methodologies for improving length of diffusion of transistors. For example, a first transistor with a first diffusion node which is bounded by a first diffusion cut is identified in a transistor level layout. The first diffusion cut is replaced with a first floating gate, and a first filler cell with a first filler diffusion region is added to extend a length of diffusion of the first diffusion node. Increasing the length of diffusion leads to improving drive strength and performance of the first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.