Inventor · Cary, NC, US

Benjamin J. Bowers

26Patents
8h-index
26Co-inventors
71Inventor score

Filing activity: Aug 27, 2001 → Jun 21, 2017

Most-cited inventions

PatentTitleAreaCited byStatus
US8782576B1 Method and apparatus for a diffusion bridged cell library Emerging Cross-Sectional Technologies 65 Active
US9070551B2 Method and apparatus for a diffusion bridged cell library Emerging Cross-Sectional Technologies 61 Active
US7343570B2 Methods, systems, and media to improve manufacturability of semiconductor devices Emerging Cross-Sectional Technologies 20 Expired
US7908571B2 Systems and media to improve manufacturability of semiconductor devices Emerging Cross-Sectional Technologies 13 Active
US8141016B2 Integrated design for manufacturing for 1×N VLSI design Physics 11 Active
US8516428B2 Methods, systems, and media to improve manufacturability of semiconductor devices Emerging Cross-Sectional Technologies 9 Active
US8122399B2 Compiler for closed-loop 1×N VLSI design Physics 9 Active
US10236302B2 Standard cell architecture for diffusion based on fin count Physics 8 Active
US7966598B2 Top level hierarchy wiring via 1×N compiler Physics 7 Active
US8156458B2 Uniquification and parent-child constructs for 1xN VLSI design Physics 6 Active
US6815984B1 Push/pull multiplexer bit Electricity 6 Expired
US8136062B2 Hierarchy reassembler for 1×N VLSI design Physics 5 Active
US8188516B2 Creating integrated circuit capacitance from gate array structures Electricity 4 Active
US10366196B2 Standard cell architecture for diffusion based on fin count Physics 4 Active
US10282503B2 Mitigating length-of-diffusion effect for logic cells and placement thereof Physics 3 Active
US8887113B2 Compiler for closed-loop 1xN VLSI design Physics 2 Active
US7672188B2 System for blocking multiple memory read port activation Physics 2 Active
US8132134B2 Closed-loop 1×N VLSI design system Physics 1 Active
US7882385B2 Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bank Electricity 1 Active
US7728362B2 Creating integrated circuit capacitance from gate array structures Electricity 1 Active
US7904847B2 CMOS circuit leakage current calculator Physics 1 Active
US9558308B2 Compiler for closed-loop 1×N VLSI design Physics 1 Active
US9306570B1 Continuous diffusion configurable standard cell architecture Electricity 1 Active
US9852080B2 Efficiently generating selection masks for row selections within indexed address spaces Physics 0 Active
US8298888B2 Creating integrated circuit capacitance from gate array structures Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.