Systems and methods for clock tree clustering
US10282506B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Oct 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, media, and other such embodiments described herein relate to generation of clock routing trees. One embodiment involves accessing a circuit design and a clock tree hierarchy input indicating a nested list of partition or sink groups, each group of the nested list of groups comprising one or more clock tree elements of a plurality of clock tree elements from the circuit design. A routing topology associated with a source and a plurality of sinks are determined based on an ordering within the nested list of partition groups. These routing directions are used in synthesizing a clock tree for the circuit design. In additional embodiments, the clock tree hierarchy input provides clustering information, port placement for connections between partition groups of the clock tree, and parameters describing limitations or criteria for individual partition groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.