Method and circuit for adaptive read-write operation in self-timed memory
US10283191B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2018 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Mar 9, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a memory circuit including a dummy word line driver driving a dummy word line, dummy memory cells coupled to a dummy bit line and a dummy complementary bit line, and a transmission gate coupled to the dummy word line to pass a word line signal from the dummy word line driver to an input of the dummy memory cells. A transistor is coupled to the dummy word line between the transmission gate and a pair of pass gates of a given one of the dummy memory cells closest to the transmission gate along the dummy word line. A reset signal output is coupled to the dummy complementary bit line. The transistor serves to lower a voltage on the dummy word line, and a reset signal indicating an end of a measured dummy cycle is generated at the reset signal output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.