Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof
US10283493B1 · kind B1 · utility
189Cited by
56References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 17, 2018 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Jan 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1434
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first die includes a three-dimensional memory device and first copper pads. A second die includes a peripheral logic circuitry containing CMOS devices located on the semiconductor substrate and second copper pads. A bonded assembly is formed by bonding the first copper pads with the second copper pads through copper interdiffusion to provide multiple bonded pairs of a respective first copper pad and a respective second copper pad at an interface between the first die and the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.