Structure and method to achieve large strain in NS without addition of stack-generated defects
US10283638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2016 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Mar 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
Abstract
A stack for a semiconductor device and a method for making the stack are disclosed. The stack comprises a plurality of sacrificial layers in which each sacrificial layer comprises a first lattice parameter; and at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter and in which each channel layer is disposed between and in contact with two sacrificial layers. The stack is formed on an underlayer in which a sacrificial layer is in contact with the underlayer. The underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.