Robert C. Bowen
29Patents
8h-index
16Co-inventors
68Inventor score
Filing activity: Dec 1, 2003 → Sep 15, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7061058B2 | Forming a retrograde well in a transistor to enhance performance of the transistor | Emerging Cross-Sectional Technologies | 122 | Expired |
| US9287357B2 | Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same | Emerging Cross-Sectional Technologies | 65 | Active |
| US9570609B2 | Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same | Electricity | 48 | Active |
| US9461114B2 | Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same | Performing Operations; Transporting | 42 | Active |
| US9647098B2 | Thermionically-overdriven tunnel FETs and methods of fabricating the same | Electricity | 33 | Active |
| US9711414B2 | Strained stacked nanosheet FETS and/or quantum well stacked nanosheet | Electricity | 31 | Active |
| US9064699B2 | Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods | Electricity | 29 | Active |
| US9793403B2 | Multi-layer fin field effect transistor devices and methods of forming the same | Electricity | 9 | Active |
| US9178045B2 | Integrated circuit devices including FinFETS and methods of forming the same | Electricity | 7 | Active |
| US9831323B2 | Structure and method to achieve compressively strained Si NS | Electricity | 7 | Active |
| US9000505B2 | Quantum electro-optical device using CMOS transistor with reverse polarity drain implant | Electricity | 6 | Active |
| US6927137B2 | Forming a retrograde well in a transistor to enhance performance of the transistor | Emerging Cross-Sectional Technologies | 5 | Expired |
| US9613907B2 | Low resistivity damascene interconnect | Electricity | 4 | Active |
| US7268399B2 | Enhanced PMOS via transverse stress | Electricity | 3 | Expired |
| US7910918B2 | Gated resonant tunneling diode | Electricity | 3 | Active |
| US10170549B2 | Strained stacked nanosheet FETs and/or quantum well stacked nanosheet | Electricity | 3 | Active |
| US9431529B2 | Confined semi-metal field effect transistor | Electricity | 2 | Active |
| US8362462B2 | Gated resonant tunneling diode | Electricity | 2 | Active |
| US9917158B2 | Device contact structures including heterojunctions for low contact resistance | Electricity | 1 | Active |
| US10283638B2 | Structure and method to achieve large strain in NS without addition of stack-generated defects | Electricity | 1 | Active |
| US9716176B2 | FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same | Electricity | 1 | Active |
| US9236444B2 | Methods of fabricating quantum well field effect transistors having multiple delta doped layers | Electricity | 1 | Active |
| US10147793B2 | FinFET devices including recessed source/drain regions having optimized depths | Electricity | 1 | Active |
| US9685509B2 | Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions | Electricity | 1 | Active |
| US9583590B2 | Integrated circuit devices including FinFETs and methods of forming the same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.