Compensated photonic device structure and fabrication method thereof
US10283665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Jun 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F30/223
Abstract
Various embodiments of a compensated photonic device structure and fabrication method thereof are described herein. A photonic device may include a silicon-on-insulator (SOI) substrate with a buried oxide (BOX) layer therein, a Si waveguide and an n-type contact layer formed on the BOX layer, a Si multiplication layer disposed on the n-type contact layer, a p-type Si charge layer disposed on the Si multiplication layer, a germanium (Ge) absorption layer disposed on the p-type Si charge layer, a p-type contact layer disposed on the Ge absorption layer, and a metal layer disposed on the p-type contact layer. A compensated region may be formed between the p-type Si charge layer and the Ge absorption layer with a portion of the compensated region in the p-type Si charge layer and another portion of the compensated region in the Ge absorption layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.