Stress isolation features for stacked dies
US10287161B2 · kind B2 · utility
3Cited by
20References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2016 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Jul 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated device package is disclosed. The package can include a carrier, such as first integrated device die, and a second integrated device die stacked on the first integrated device die. The package can include a buffer layer which coats at least a portion of an exterior surface of the first integrated device die and which is disposed between the second integrated device die and the first integrated device die. The buffer layer can comprise a pattern to reduce transmission of stresses between the first integrated device die and the second integrated device die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.