Apparatus and method for increasing resilience to faults
US10289332B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2017 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | May 3, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are provided for increasing resilience to faults. The apparatus comprises processing circuitry for executing a plurality of code sequences including at least one critical code sequence, and configuration storage for storing mode control data for the processing circuitry. When the processing circuitry is executing a critical code sequence, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry, where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry. By increasing the resilience to faults, this reduces the chance that any such fault will manifest itself as an error in the processing operations being performed by the apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.