Iterative division with reduced latency
US10289386B2 · kind B2 · utility
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4References
11Claims
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Key dates
| Filing date | Apr 21, 2016 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Apr 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplier unit may be configured to generate a final approximation of an iterative arithmetic operation performed on two operands. Circuitry coupled to the multiplier unit may perform a shift operation and a mask operation on the final approximation to generate shifted and un-shifted approximations, respectively. The circuitry may generate a first remainder using the un-shifted approximation and a sign value of a second remainder using the first remainder. Using the sign value of the second remainder, the circuitry may perform a rounding operation on the shifted approximation to generate a final answer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.