Memory with pattern oriented error correction code
US10289486B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2017 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Jul 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for parity generations in error-correcting code (ECC) memory to reduce chip areas and test time in imaging system are disclosed herein. Memory tests are needed to catch hard failures and soft errors. Random and nondestructive errors are soft errors and are undesirable. Soft errors can be detected and corrected by the disclosed ECC which is based on Hamming code. Before data are written into memory, the first parity generator based on the disclosed ECC generates the first parity by calculating the data. The first parity and data are stored into the ECC memory as a composite word. When the previously stored word is fetched from the ECC memory, the second parity generator based on the disclosed ECC is used to generate the second parity. A comparison between the first and second parity leads to a disclosed error mask, which is used to correct a single bit error if the error only happens to a single bit of the fetched data. A minimum distance of three in the disclosed ECC is maintained to make certain that a single bit is corrected on the read data to retrieve the originally stored memory data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.