NMONITOR instruction for monitoring a plurality of addresses
US10289516B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2016 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Feb 7, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core includes a decode circuit to decode an instruction, where the instruction specifies an address to be monitored. The processor core further includes a monitor circuit, where the monitor circuit includes a data structure to store a plurality of entries for addresses that are being monitored by the monitor circuit and a triggered queue, where the monitor circuit is to enqueue an address being monitored by the monitor circuit into the triggered queue in response to a determination that a triggering event for the address being monitored by the monitor circuit occurred. The processor core further includes an execution circuit to execute the decoded instruction to add an entry for the specified address to be monitored into the data structure and ensure, using a cache coherence protocol, that a coherency status of a cache line corresponding to the specified address to be monitored is in a shared state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.