Wim Heirman
14Patents
2h-index
15Co-inventors
43Inventor score
Filing activity: Jun 17, 2013 → Dec 23, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10929132B1 | Systems and methods for ISA support for indirect loads and stores for efficiently accessing compressed lists in graph applications | Physics | 5 | Active |
| US10303609B2 | Independent tuning of multiple hardware prefetchers | Physics | 2 | Active |
| US10394678B2 | Wait and poll instructions for monitoring a plurality of addresses | Emerging Cross-Sectional Technologies | 2 | Active |
| US10489297B2 | Prefetching time allocation | Physics | 1 | Active |
| US10684858B2 | Indirect memory fetcher | Physics | 1 | Active |
| US10621099B2 | Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristics | Physics | 0 | Active |
| US12333305B2 | Delayed cache writeback instructions for improved data sharing in manycore processors | Physics | 0 | Active |
| US12050915B2 | Instruction and logic for code prefetching | Physics | 0 | Active |
| US11256626B2 | Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristics | Physics | 0 | Active |
| US10289516B2 | NMONITOR instruction for monitoring a plurality of addresses | Emerging Cross-Sectional Technologies | 0 | Active |
| US11010182B2 | Instruction window centric processor simulation | Physics | 0 | Active |
| US10877886B2 | Storing cache lines in dedicated cache of an idle core | Physics | 0 | Active |
| US10942851B2 | System, apparatus and method for dynamic automatic sub-cacheline granularity memory access control | Emerging Cross-Sectional Technologies | 0 | Active |
| US12111772B2 | Device, system and method for selectively dropping software prefetch instructions | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.