Patent · US Active

Systems and methods for assigning clock taps based on timing

US10289775B1 · kind B1 · utility

2Cited by

5References

19Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Brian Wilson · Pleasant Hill, US
Charles J. Alpert · Cedar Park, US
Zhuo Li · Austin, US

Key dates

Filing date	Sep 1, 2017
Grant date	May 14, 2019
Priority date	—
Expiry date	Sep 15, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various embodiments described herein assign, within a circuit design, a clock tap to a clock device (e.g., flip-flop) to improve timing of a path between the clock tap and the clock device. In particular, some embodiments identify which clock devices should be assigned to a clock tap so as to improve final timing as seen under an on-chip variation timing analysis, such an AOCV/CPPR (advanced on-chip variation/common clock path pessimism removal) timing analysis. Some such embodiments may achieve this by identifying, after post-route-optimization, critical clock-tap-to-clock-device assignments based on timing analysis results (e.g., from AOCV/CPPR timing analysis) and feeding back those critical clock-tap-to-clock-device assignments to a process performing new clock tap assignments.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.