Memory devices that sample latch trip voltages prior to reading data into latches and methods of operating same
US10290343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2017 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | May 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.