Semiconductor device
US10290641B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2018 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Jan 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a 6T SRAM cell formed on a substrate. The SRAM cell includes a first and a second PMOS transistors formed over an N-well line in a substrate. A first and a second NMOS transistors are formed over a first P-well line in the substrate at a first side of the N-well line. A third and a fourth NMOS transistors are formed over a second P-well line in the substrate at a second side of the N-well line. A first gate line connects gates of the first PMOS transistor and the first NMOS transistor. A second gate line connects a gate of the second NMOS transistor. A third gate line connects gates of the second PMOS transistor and the third NMOS transistor. A fourth gate line connects a gate of the fourth NMOS transistor. The first gate line and the third gate line are in L-shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.