Three-dimensional memory device with graded word lines and methods of making the same
US10290652B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2018 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | May 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a three-dimensional memory device includes providing an alternating stack of insulating layers and sacrificial material layers located between a first trench and a second trench, forming memory stack structures extending vertically through the alternating stack, wherein each of the memory stack structures contains a memory film and a vertical semiconductor channel, removing the sacrificial material layers selective to the insulating layers through the first and the second trenches to form backside recesses having a first proximal region adjacent to the first trench, a second proximal region adjacent to the second trench and a distal region located between the first and the second proximal regions, and forming fluorine-free tungsten layers in the respective backside recesses such that each fluorine-free tungsten layer has a greater thickness in the distal region than in the first and the second proximal regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.