Metal-oxide-semiconductor transistor and method of forming gate layout
US10290718B2 · kind B2 · utility
0Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2017 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Aug 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320 nanometers, and the metal gate has at least one plug hole. The metal-oxide semiconductor transistor further includes at least one insulating plug disposed in the plug hole and two diffusion regions disposed respectively at two sides of the metal gate in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.