System and method for biasing an RF circuit
US10291194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2017 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Oct 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/61
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In accordance with an embodiment, a circuit includes: a replica input transistor, a first replica cascode transistor, an active current source, and an active cascode biasing circuit. The active current source is configured to set a current flowing through the first replica cascode transistor and the replica input transistor to a predetermined value by adjusting a voltage of a control node of the replica input transistor; and an active cascode biasing circuit including a first output coupled to the control node of the first replica cascode transistor, and the active cascode biasing circuit configured to set a drain voltage of the replica input transistor to a predetermined voltage by adjusting a voltage of the control node of the first replica cascode transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.