Chopping switch time-skew calibration in time-interleaved analog-to-digital converters
US10291247B1 · kind B1 · utility
6Cited by
15References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2018 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Mar 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.