Clock management using full handshaking
US10296065B2 · kind B2 · utility
6Cited by
40References
25Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 25, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Apr 15, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.