Low-area fixed-point polynomials
US10296293B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Jun 27, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Jun 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of implementing fixed-point polynomials in hardware logic include distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial by solving an optimization problem that outputs an accuracy parameter and a precision parameter for each node. Each operator is then itself optimized to satisfy the part of the error bound allocated to that operator and as defined by the accuracy and precision parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.