Method and apparatus for performing a vector bit gather
US10296334B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2014 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Apr 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, method, and system for performing a vector bit gather are describe herein. One embodiment of a processor includes: a first vector register storing one or more source data elements, a second vector register storing one or more control elements, and a vector bit gather logic. Each of the control elements includes a plurality of bit fields, each of which is associated with a plurality of corresponding bit positions in a destination vector register and is to identify a bit from the one or more corresponding source data element to be copied to each of the plurality of corresponding bit positions. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a bit from the source data elements and responsively copy it to each of the plurality of corresponding bit positions in the destination vector register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.