Hybrid atomicity support for a binary translation based microprocessor
US10296343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Jun 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device including a first shadow register, a second shadow register, and an instruction execution circuit, communicatively coupled to the first shadow register and the second shadow register, to receive a sequence of instructions comprising a first local commit marker, a first global commit marker, and a first register access instruction referencing an architectural register, speculatively execute the first register access instruction to generate a speculative register state value associated with a physical register, responsive to identifying the first local commit marker, store, in the first shadow register, the speculative register state value, and responsive to identifying the first global commit marker, store, in the second shadow register, the speculative register state value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.