Computer vision processing in hardware data paths
US10296351B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | May 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8053
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a processor and a coprocessor. The processor may be configured to generate a command to run a directed acyclic graph. The coprocessor may be configured to (i) receive the command from the processor, (ii) parse the directed acyclic graph into a data flow including one or more operators, (iii) schedule the operators in one or more data paths and (iv) generate one or more output vectors by processing one or more input vectors in the data paths. The data paths may be implemented with a plurality of hardware engines. The hardware engines may operate in parallel to each other. The coprocessor may be implemented solely in hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.