Patent · US Active

Automated bottom-up and top-down partitioned design synthesis

US10296689B2 · kind B2 · utility

0Cited by

20References

20Claims

0Family size

Assignee

SYNOPSYS, INC. · US

Inventors

Smita Bakshi · Los Gatos, US
Kenneth S. McElvain · Los Altos, US
Gael Paul · Palo Alto, US

Key dates

Filing date	Jul 2, 2014
Grant date	May 21, 2019
Priority date	—
Expiry date	Aug 13, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.