Implementing circuit designs adapted for partial reconfiguration
US10296699B1 · kind B1 · utility
2Cited by
4References
18Claims
0Family size
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Key dates
| Filing date | Mar 23, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Mar 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementing a circuit design for partial reconfiguration can include routing, using a processor, a net of the circuit design that connects an endpoint within a reconfigurable module with an endpoint within static circuitry external to the reconfigurable module and forming, using the processor, a set of candidate nodes including nodes used to route the net. A node from the set of candidate nodes is determined as the partition pin for partial reconfiguration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.