Engineered substrate structure for power and RF applications
US10297445B2 · kind B2 · utility
8Cited by
5References
15Claims
0Family size
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Key dates
| Filing date | Jun 13, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Jun 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate includes a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion layer. The substrate also includes a silicon oxide layer coupled to the support structure, a substantially single crystalline silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystalline silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.