Stacked vertical NFET and PFET
US10297513B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Dec 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0186
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides stacked VFET devices. In one aspect, a method of forming a stacked VFET device includes: patterning a fin(s) in a wafer having a vertical fin channel of a VFET1 separated from a vertical fin channel of a VFET2 by an insulator; forming a bottom source and drain of the VFET1 below the vertical fin channel of the VFET1; forming a gate of the VFET1 alongside the vertical fin channel of the VFET1; forming a gate of the VFET2 alongside the vertical fin channel of the VFET2; forming a top source and drain of the VFET1 above the vertical fin channel of the VFET1; forming a bottom source and drain of the VFET2 below the vertical fin channel of the VFET2; and forming a top source and drain of the VFET2 above the vertical fin channel of the VFET2. A stacked VFET device is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.