Methods for processing a 3D semiconductor device
US10297586B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2018 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | May 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for processing a 3D semiconductor device, the method including: providing a wafer including a plurality of first dies, the plurality of first dies including a first transistor layer and a first interconnection layer; completing a step of transferring a plurality of second dies each overlaying at least one of the first dies, where each of the plurality of second dies includes a second transistor layer, where at least one of the plurality of first dies is substantially larger in area than at least one of the plurality of second dies, and where each of the plurality of second dies has a thickness greater than six microns; and completing a step of thinning the plurality of second dies, where each of the plurality of second dies has a thickness of less than 2 microns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.